1. Field of the Invention
The present invention relates to a semiconductor device applied to a variable capacitance capacitor and amplifier for use in an analog circuit for example.
2. Description of the Related Art
A voltage controlled oscillator includes a capacitor of a variable capacitance and can generate an oscillation signal of a predetermined frequency by varying the capacitance of the variable capacitor. The voltage controlled oscillator needs a high Q value so as to reduce phase noise. In order to achieve this, a lower parasitic capacitance and lower parasitic resistance are needed as the characteristics of the variable capacitor.
Generally, a variable capacitor is constructed by using a junction portion of a P+ type semiconductor layer formed in an N type well area or a junction portion of an N+ layer formed in a P type well area.
FIG. 17 shows one practical form of a capacitor of a variable capacitance using an N type well area. For example, an N type well area 101 is formed in a surface area of, for example, a P type semiconductor substrate 100. In the N type well area 101, a P+ type semiconductor layer 102 and N+ type semiconductor layer 103 are provided. A variable capacitance capacitor 104 is constructed by using a junction portion of the P+ type semiconductor layer 102 and N type well area 101. A connection line 105 is connected to the respective semiconductor layers 102 and 103. In the variable capacitor 104, a capacitance 106 between connection lines 105 is dominant as a parasitic capacitance and, as a parasitic resistance, a connection line resistance (not shown) and well area resistance (hereinafter referred to also as a “well resistance”) are dominant.
As a result of advances in the design rule of the device, a smaller space can be achieved between the P+ type semiconductor layer 102 and the N+ type semiconductor layer 103. Owing to this, it is possible to reduce the parasitic resistance of the well area 101. Where, however, the space between the P+ type semiconductor layer 102 and the N+ semiconductor layer 103 is made smaller, a distance between the connection lines 105 is made narrower. As a result, a connection line-to-connection line capacitance 106 as a parasitic capacitance is increased.
FIG. 18 shows a variance state between the capacitance and a bias voltage applied between the P+ type semiconductor layer 102 and the N+ semiconductor layer 103. As shown in FIG. 18, when the parasitic capacitance increases, the range of the capacitance responsive to the bias voltage is lowered. In order to reduce the connection line-to-connection line capacitance, therefore, it is necessary to broaden the space between the P+ type semiconductor layer 102 and the N+ semiconductor layer 103 and, thereby, to form a variable capacitance capacitor. This means that the well resistance cannot be lowered.
On the other hand, the parasitic resistance is a source of thermal noise, and is proportional to the resistance. This causes a lowering in Q value in the voltage controlled oscillator for example and causes a degeneration resulting from the phase noise.
Further, as shown in FIG. 19, a MOS transistor (hereinafter referred to as a MOSFET) in an amplifier, being greater in the resistance of a P type well area 110, causes a power loss and it is difficult to construct a high gain amplifier. In general, this type of amplifier is mounted in combination with a digital circuit. However, the resistance of the well used in a current digital circuits lowers the gain of the amplifier.
FIG. 20 shows a relation of the well resistance to the gain. In the current analog/digital hybrid semiconductor devices, the resistive value of the well used in the digital section is, for example, 50 Ω. In the case of the well resistance, it is difficult to obtain a high gain. As is evident from this figure, in order to raise the gain, it is necessary that the well resistance be raised or lowered. It may be considered that, in order to raise the well resistance, use is made of a high resistance substrate. However, there occurs, for example, a problem, such as a slip in the wafer. It may also be considered that, in order to lower the well resistance, use is made of a low resistance substrate.
FIG. 21 shows one practical form of an analog/digital hybrid semiconductor device using a low resistance substrate. Well areas 121 and 122 are formed in a P+ substrate 120 serving as a low resistance substrate and, in the well areas 121 and 122, an analog circuit and digital circuit are formed. In this way, the well resistance can be lowered in the case of using the low resistance substrate. In the case of lowering the well resistance, noise from the digital circuit enters the analog circuit, thus exerting an adverse effect on the characteristics of the analog circuit.
FIG. 22 shows the relation between the well resistance and amount of intruding noise. As evident from the above, the higher the amount of intruding noise, the lower the well resistance. In an analog/digital hybrid semiconductor device, it is thus not possible to adopt a low resistance substrate.
A semiconductor device is therefore desired which is capable of improving the characteristics of the circuit elements by setting the resistive value of the well in accordance with the kinds of the circuit elements.